A CMOS imager circuit includes a focal plane array of pixel cells, each one of the cells including a photosensor, for example, a photogate, photoconductor, or a photodiode overlying a substrate for accumulating photo-generated charge in the underlying portion of the substrate. Each pixel cell has a charge storage region, formed on or in the substrate, which is connected to a gate of an output transistor that is part of a readout circuit. The charge storage region may be constructed as a floating diffusion region. In some imager circuits, each pixel cell may include at least one electronic device such as a transistor for transferring charge from the photosensor to the storage region and one device, also typically a transistor, for resetting the storage region to a predetermined charge level prior to charge transference.
In a CMOS imager, the active elements of a pixel cell perform the necessary functions of: (1) photon to charge conversion; (2) accumulation of image charge; (3) resetting the storage region to a known state before the transfer of charge to it; (4) transfer of charge to the storage region accompanied by charge amplification; (5) selection of a pixel for readout; and (6) output and amplification of a signals representing pixel charge and pixel reset states. Photo charge may be amplified when it moves from the initial charge accumulation region to the storage region. The charge at the storage region is typically converted to a pixel output voltage by a source follower output transistor.
CMOS imagers of the type discussed above are generally known, as discussed, for example, in U.S. Pat. No. 6,140,630, U.S. Pat. No. 6,376,868, U.S. Pat. No. 6,310,366, U.S. Pat. No. 6,326,652, U.S. Pat. No. 6,204,524, and U.S. Pat. No. 6,333,205, all assigned to Micron Technology, Inc.
FIG. 1A illustrates a conventional imager implementing a serial readout for the pixel signals in the columns of array 101. Programmable gain amplifier 105 and a serial analog-to-digital converter 106 receive the column pixel signals in sequence. In a CMOS imager, each sample-and-hold circuit 102 typically samples and holds a reset Vrst and a photo Vsig signal for a respective pixel of an array 101 row being read. The programmable gain amplifier 105 typically includes a differential amplifier for subtracting the Vrst and Vsig signals and supplying the result to a downstream processing circuit. Thus, pixel signals from all columns of the pixel array 101 are output in series to a single gain amplifier 105 and analog-to-digital converter 106. The illustrated imager includes one sample-and-hold circuit 102 for each column. Optionally, a column amplifier may be provided between each sample-and-hold circuit 102 and a respective column of pixel array 101. The sample-and-hold circuits 102 are selectively coupled, one at a time, to the programmable gain amplifier 105 via a multiplexer 103 controlled by a column scanner 104. The serial readout scheme depicted in FIG. 1A has several advantages. For example, the scheme is easy to design and optimize and well-suited for small imagers.
Serial readout schemes are not, however, well-suited for use in large-format or high-speed imaging applications where a pixel array 101 may contain thousands of columns. One drawback is readout speed, which is limited by the throughput of the gain amplifier 105 and the analog-to-digital converter 106. In addition, the high data throughput rate in large-format, high-speed image sensors makes current consumption unacceptably high and chips unacceptably large due, in part, to the switched-capacitor circuits used in the readout circuitry of most high-precision imagers. Switched-capacitor circuits are typically used in the pixel readout analog path, including column sample-and-hold circuit 102, programmable gain amplifier 105, which typically includes a differential amplifier for subtracting the Vrst and Vsig signals, and additional amplifier stages of analog-to-digital converter 106.
FIG. 2 is a general graph representing the settling time of a switched-capacitor circuit, which may be used, for example, in the readout circuitry of the imager illustrated in FIG. 1A. FIG. 2 illustrates an exponential gain-bandwidth (GBW) limited settling time and a slew rate limited settling time. In high-speed circuits, the operational amplifier current required by the GBW of a switched-capacitor circuit is often higher than that required by the slew rate. In other words, GBW limited settling is dominant, and current consumption has a quadratic dependence to sampling rate. In slow- and medium-speed circuits, slew rate limited settling is dominant, and current consumption is linearly dependent on the clock frequency. Thus, the settling time in high-speed circuits can be undesirably long and reduce throughput, creating a bottleneck in a serial readout scheme, such as the scheme illustrated in FIG. 1A.
Serial readout schemes also suffer from increased noise and power consumption due to large parasitic capacitance, mainly coming from the column select switches of multiplexer 103 and long video lines connecting the column select switches to the input of the programmable gain amplifier 105. This large parasitic capacitance dramatically reduces the feedback factor of the gain amplifier 105 and increases the power required to operate it, while simultaneously increasing amplifier noise and offset as well as digital crosstalk or interference in the video line. Variations in column sampling capacitance, mainly due to inhomogeneous thickness of the capacitor dielectric film, also contribute to fixed pattern noise or shading.
In contrast to the serial readout scheme described above with reference to FIG. 1A, a “simple column parallel” readout architecture comprises dedicated readout circuitry for each column of a pixel array 111, as shown in FIG. 1B. The per-column readout circuitry typically comprises a sample-and-hold circuit 112, a gain amplifier 113, and an analog-to-digital converter 114. Generally, the gain amplifier 113 includes a function for subtracting the Vrst and Vsig signals. Optionally, the column sample-and-hold circuit 112 and gain amplifier 113 may be combined. The outputs from the readout circuits may be stored in a digital line memory 115 and subsequently output to an image processor (not shown).
Although column parallel readout architectures overcome some of the readout bottlenecks and parasitic capacitance issues associated with serial readout architectures, implementing an analog-to-digital converter 114 for every column is problematic because the size of each analog-to-digital converter 114 is constrained to the width of a single column of the pixel array 111. Single-slope analog-to-digital converters (also called “ramp analog-to-digital converters”) are often used in per-column implementations because the many analog-to-digital converters can share a common ramp signal. Thus, only a comparator and a latch have to be implemented in every column. However, the large number of analog-to-digital converters requires more power to operate than a serial readout scheme employing only one analog-to-digital converter. Moreover, since the conversion cycles of single-slope analog-to-digital converters increase exponentially with resolution, parallel readout architectures, such as the one illustrated in FIG. 1B, are not suitable for high-accuracy applications because of the difficulty associated with designing sufficiently low-offset, low-delay, and low-power comparators that fit within a single column width.
Other kinds of analog-to-digital converters having a simpler architecture with fewer conversion cycles, and therefore lower resolution, may also be used. For example, successive approximation register (SAR) and algorithm (or “cyclic”) analog-to-digital converters can also be configured to fit within a single column width, as required by column parallel readout architectures. However, to obtain high accuracy, SAR and cyclic analog-to-digital converters must be relatively large, since their accuracy is determined by capacitor mismatching. Therefore, it is difficult to realize high conversion accuracy in a column parallel readout scheme because large-value capacitors and high-performance comparators cannot be readily implemented within a single column width. Moreover, column parallel readout schemes are undesirable because they require a customized design that must be redesigned whenever pixel size, and consequently column width, is scaled down. Fixed pattern noise from gain/offset mismatching between columns is also a concern.
Recently, a multi-channel serial readout architecture, which comprises several analog-to-digital converters and gain amplifiers, as shown in FIG. 1C, has been used in large-format imagers to improve throughput. Similar to the readout architectures described above, a sample-and-hold circuit 122 is coupled to each column of a pixel array 121. A multiplexer 123 controlled by a column scanner 124 selectively couples the sample-and-hold circuits 122 to one of several readout channels. Each readout channel comprises a programmable gain amplifier 125 and an analog-to-digital converter 126. Because readout channels can be flexibly arranged anywhere on the chip close to the column sample-and-hold circuit 122 and multiplexer 123, many limitations of the column parallel readout architecture discussed above are alleviated. However, the long video lines 123a of multiplexer 123, create substantial parasitic capacitance and, therefore, the multi-channel serial readout scheme suffers from the same noise limitations as the simple serial readout scheme described above with reference to FIG. 1A. Furthermore, parasitic capacitance between adjacent channels will lead to crosstalk and generate artifacts in the resulting image. Column fixed pattern noise resulting from channel mismatching is also a concern.
There is a need in the art for an efficient readout architecture that can easily be scaled to accommodate imagers with reduced pixel pitch and provides the higher throughput associated with existing parallel readout architectures while simultaneously providing the improved image quality and reduced power consumption associated with serial readout architectures.